13 December

Written Test Question for Physical Design Engineer: Question Set - 6


 Code: ALTRN0Y112020PD

Some companies take a written test sometimes to shortlist the candidates before the interview process. This is a common process if the applicants are large in numbers. In such written test, the format is MCQ and some short questions. 

We are very thankful to one of our follower who has appeared in this test and shared these questions based on memory. The purpose of sharing this question is only to provide the right guidance to the candidate who is going to appear in such a written test. I would encourage all the freshers to practice these question for their future test/Interview. I would also encourage to find the answer to these question either by own. There is no sense of proving the answer to these questions here. But if someone finds any question really difficult to solve and open discussion in the comment section. 

1. Hold slack equation 

2. Setup slack equation
3. When did hold analysis depends on the frequency of the clock 
a) half cycle path
b) single cycle path 
C) multicycle path 
d) it never depends 

4. While doing OCV which things are considered for setup analysis 
a) max launch path delay and min capture path delay
b) min launch path delay and max capture path delay 
c) max launch and capture path delay
d) min launch and capture path delay 

5. How to fix EM effect 
a) decreasing the space between metal layers 
b) decreasing straps 
c) increasing drive strength of the driver 
d) increasing space between metal layers 

6. Why do we add tap cells 
a) to maintain well continuity 
b) to prevent latch up  
c) to prevent DRC's 
d) all of the above 

7. Why do we add metal fillers 
a) to ensure etching properly 
b) to ensure density issues 
c) to increase the area of the chip 
d)to ensure well continuity 

8. If the schematic has 11 and layout is 10 nets then, what might be reason 
a) opens 
b) shorts
c) ERC
d) all of the above 

9. Numerical problem related to finding clock frequency 

10. Numerical problem related to finding slack 

11. High positive skew leads to
a) setup violation 
b) hold violation 
c) DRcs
d) all of the above 

12. In VLSI Design, CMP stands for? 

13. Numerical problem to find setup slack 

14. Nand and Nor gate logic diagram SOP forms

15. Setup uncertainty increases from placement to CTs
a) true 
b) false
c) based on SDC 
d) based on clock frequency 

16. Only clearing LVS leads to the proper functioning of the chip 
a) true 
b) false 

17. Numerical problem related to reg to reg data path delay calculation 

18. A CMOS circuit consumes only a significant amount of power during 
a) static state 
b) when cooling 
c) when warming
d) all of the above 

19. Routing congestion depends on which factors
a) ratio of required layers and available layers 
b) ratio of available and required 
c) depending on availability of metalayers 
d) none of the above 

20. Question related to ground bounce, power bounce and glitch 

21. Value of threshold voltage depends on
a) doping concentration 
b)distance between source and drain 
c) temperature 
d) all of the above 

22. Why we reorder scan chains during placement stage?

23. For multi-voltage blocks which power cells are used 
a) isolation cells
b) retention cells 
c) level shifters 
d) all

24. Which configuration is more preferable for floorplan 
a) double BACK  + channel width spacing 
b) without double back + channel width spacing 
c) double back + row alignment
d) none of the above 

25. Concept of fixing time violations by adjusting clock arrival times at the registers in the preCTS stage is called 
a) time borrowing 
b) managing skew 
c) maintaining timing 
d) none of the above 

26. While calculating standard cell utilization what are all will be considered 
a) macro + blockage + standard cell (area)
b) macro + blockage (area)
c) macro + physical cells + standard cells (area)
d) all of the above 

27. RV checks Are needed for 

28. Inputs for LVS
a) spice + netlist + rule deck
b) spice + rule deck + lib files 
c) OASIS + netlist + lib 
d) none of the above 

29. Via3 will connect which of the following metal layers 
a) 1 and 3
b) 2 and 3
c) 3 and 4
d) none 


30.  A 4-bit modulo 16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50 ns. The max. clock frequency that can be used is equal to

31. A pulse has a period of 15 ms. Its frequency is

32. A 8-bit successive approximation ADC has a full-scale reading of 2.55 volts and its conversion time for an analog input of 1 volt is 20 ┬Ás. The conversion time for a 2 volts input will be?

33 . How many binary numbers are required to represent a decimal number 748?

 34. DRC is used to 
a)to ensure chip fabrication
b)to ensure chip doesn't get heated 
c)to verify parasitics on chip
d) all of these 

35.  Antenna diodes are used for 
a) to protect the gate 
b) protect VDD and VSS
c) to protect the substrate 
d) all of the above

36.  Buffers are added to 
a) to fix timing violations 
b) to fix DRC
c) to fix parasitic values 
d) all 

37. Metal pitch and metal spacing are the same 

38. What is the effect of high drive strength buffer when added in the long net 
a) delay of net decreases
b) delay of net increases 
c) delay doesn't effect 
d) none of the above 

39. Cross talk glitch leads to 
a)timing failure 
b) functional failure 
c) substrate failure 
d)all of these 

40. Programmable special cells used during ECO
a) gate array filler cells
b) filler cells
c) metal fills 
d)decap cells 

41. What is a physical cell?
a) cell which doesn't have any functionality 
b)  cell is not synthesized 
c) cell which is inserted only in layout 
d) all of the above 

42. Power gating technique in low power is used to reduce 
a)static power 
b)leakage power 
c)internal power 
d) all of the above 

43. Which of the following is not present in SDC 
a) max cap
b) max trans 
c) max current density 
d) max fanout 

44. The phenomenon associated with transistor switching when the gate voltage may appear less than the local ground potential 
a) ground bounce 
b) supply bounce
c) glitch 
D) none 

45. Leakage recovery can be achieved through 
a)Hvt to Svt
b) Lvt to Hvt
C)Rvt to Lvt.
d) svt to lvt

46. Which of the following must be fixed during physical design 
a) floating inputs 
b) floating outputs 
C) floating metals 
d) both b and c 

47. Which slew value will be propagated to slew _out of slew _A is 100 ps and slew_B is 80ps for hold analysis 
a) 80 ps
b) 100 ps
c) 20 pls
d) 180 ps

48. A 16-bit modulo 16 ripple counter uses JK flops if propagation delay is 25 ns, the max frequency of the clock is 
a) 25
b) 10
c) 2
d) 16

49. Digital signals transmitted on a single conductor must be transmitted in 
a) serial 
b) digital 
C) slow speed 
d) none 

50. In a certain digital waveform, the period is four times the pulse width, the duty cycle of the waveform will be? 

51. Follow pin connections to the standard s are done in encounter through
a)z- route 
c)trail route 
d) nano- route 

52.set Y[ ]; 
set Z[a,b,c]; 
lappend $Y,$Z;
What is the output 
a) empty list 
b) [a b]
c) [a b c]
d) none

[ Note: If you find any question has typo error or wrong, comment for the correction.]

 Thank you.

Synthesis and Physical Design Interview Questions: Question Set -5

Code: CYPR2Y102020PD

Introduction and Experiences

  1. Self Introduction
  2. Explain about the projects that you have worked on. (Type of work and tools used)


  1. Explain about Synthesis flow and what happens at each stage. (Inputs required, elaboration, generic stage, mapping and optimization stages)
  2. Explain about Synthesis Inputs. 
  3. Differentiate between Logical and Physical Synthesis. (QoR impact between them)
  4. Wire load model(WLM), Mode, Types of trees
  5. Delay Calculation in WLM method. (Fanout based delay calculation)


Place and Route

  1. What are Inputs for PnR and Initial Checks need to be done?
  2. How to check for uniqueness of Netlist?
  3. Explain stages in PnR.
  4. Explain about useful skew and how it impacts the design.
  5. How do we achieve a better insertion delay?
  6. Explain about the CTS issues that you solved.
  7. Explain Physical Cells at the transistor level.
  8. Explain UPF, power domains, supply sets, isolation cells, retention registers.
  9. Feedthru insertion procedure and minimizing them. How you did Partitioning and improved partition related size, ports creation, Congestion.


  1. RTL Code for synchronous rst and asynchronous rst. (How do we write always block for this?)
  2. How do you write RTL code for FSM? (Explain about the number of always blocks required and significance of each one)
  3. Write RTL code for the traffic light system.


  1. Explain about the LEC procedure and issues faced and solved with respect to non-equivalent points.
  2. How do we fix Setup and Hold time violations?
  3. Explain about Dynamic and Leakage Power Consumption and methods to reduce them.
  4. If the chip is fabricated and hold violation exists. So what will you do? (other than saying that chip won't work)
  5. Scripting related to finding empty modules, Unix commands.

Post Credit: 

These questions are shared by one of our active group members. Thanks a lot for your contribution!!!