31 May

Synopsys Design Constraints | SDC File in VLSI

SDC is a short form of "Synopsys Design Constraint". SDC is a common format for constraining the design which is supported by almost all Synthesis, PnR and other tools. Generally, timing, power and area constraints of design are provided through the SDC file and this file has extension .sdc. 

SDC file syntax is based on TCL format and all commands of sdc file follow the TCL syntax. In sdc file '#' is used to comment a line and '\' is used to break the line. SDC file can be generated by the synthesis tool and the same can be used in for PnR.

Constraints in SDC file

Inside the sdc file, some important constraints are as follow.

1. SDC Version: 

This statement specifies the version of the SDC file. it could be 2.1, 2.0, 1.9 or more older.

Version 2.1 has introduced in December 2017.

set sdc_version 2.1

2. Units: 

Units of various quantities like time, resistance, capacitance, voltage, current, and power can be specified using set_unit command.

Multiples units can be set using a single set_unit command.

set_units -time ns -resistance Kohm -capacitance pF -voltage V -current mA

SDC commands could be further categories as follow. Some important commands will be discussed in the later section.

A.  Operating Conditions

B.  Wire Load Models

C.  System Interface

Let's discuss some important System Interface constraints in this section.

3. Set driving cells: 

specifies the drive characteristics of input or inout ports that are driven by the cells in the technology library. These commands associate a library pin with input ports so that delay calculation can be accurately modelled.


set_driving_load [-lib_cell lib_cell_name] [-library lib_name] [-rise] [-fall] [-min] [-max] [-pin pin_name] [-from_pin from_pin_name] [-dont_scale] [-no_design_rule] [-input_transition_rise rtrans] [-input_transition_fall ftrans] [-multiply_by_facrtor] [-clock clock_name] [-clock_fall] port_list 


set_driving_cell -lib_cell IV {I1}
set_driving_cell -lib_cell AND2 -pin Z -from_pin B {I2} 

4. Set load: 

This command sets the load attributes on the specified ports and the nets in the current design. Unit of load value will be the unit of capacitance specified in the unit defined in this file.


set_load value objects [-subtract_pin_load] [-min] [-max] [[-pin_load] [-wire_load]]

set_load -pin_load 0.001 [get_ports {port[10]}]

D.  Design Rule Constraints

In this part basically maximum fanout, maximum and minimum capacitance,  and  maximum transition time are set

5. Set maximum fanout: 

Maximum fanout load is set to a specific input port and/or design


set_max_fanout fanout_value object_list 

set_max_fanout 5 [get_ports {port[10]}]

6. Set maximum transition: 

Maximum transition time is set by this command which is a design rule and set to clock port or design is set to a specific input port and/or design.


set_max_transition transition_value [-data_path] [-clock_path] object_list 

set_max_transition 2.5 [get_ports IN]

E.  Timing Constraints

In this part basically, we set clocks definition, clock group, clock latency, clock uncertainty, clock transition, input delay, output delay, timing derates etc.

7. Create clock: 


create_clock [-name clock_name] [clock_sources] [-period value] [-waveform edge_list] [-add] [-comment] 

The create_clock command creates a clock object in the current design. This command defines the specified source_objects as a clock source.


create_clock "u13/z" -name "CLK" -period 30 -waveform {12.0 27.0}
create_clock -name "PH12" -period 10 -waveform {0.0 5.0}

8. Create generated clock: 


create_generated_clock [-name clock_name] [-add] source_objects -source master_pin [-master_clock clock] [-divide_by divide_factor | -multiply_by multiply_factor ] [-duty_cycle percent] [-invert] [-preinvert] [-edges edge_list] [-edge_shift edge_shift_list] [-combinational]

The create_generated_clock command creates a generated clock object. A pin or port could be specified for the generated clock object. Generated clock follow the master clock, so whenever the master clock changes generated clock will change automatically. A generated clock can be created as a frequency-divided clock,  a frequency multiplied clock, an edge divided clock or an inverted clock.


create_generated_clock -multiplied_by 3 -source CLK [get_pins div3/Q]

The above example will generate a clock which is derived from the original clock named CLK. The generated clock will have a frequency 3 times of the original clock and time period will be one-third of the original (15ns --> 5ns).

9. Group path:


group_path [-weight weight_value] [-critical_range range_value] -default | -name group_name [-from from_list | -rise_from rise_from_list | -fall_from fall_from_list] [-through trough_list | -rise_through rise_through_list -fall_through fall_through_list] [-to to_list | -rise_to rise_to_list | -fall_to fall_to_list] [-comment comment_string] [-priority priority_level]

Groups are a set of paths or endpoints for the cost function calculations. The group enables us to specify a set of paths to optimize even though there may be a larger violation in other groups. When endpoints have specified all paths leading to those end paths are grouped. 

The create_clock command automatically creates a group for the new clock with a weight of 1.0 and named the same as the clock name. 


group_path -name "group1" -weight 2.0 -to {CLK1A CLK1B}

group_path -name GROUP1 -from [get_ports ABC/in3] -to [get-ports FF1/D]

 10. Clock uncertainty:


set_clock_uncertainity [object_list | -from from_clock | -rise_from rise_from_clock | -fall_from fall_from_clock -to to_clock | -rise_to rise_to_clock | -fall_to fall_to_clock] [rise] [-fall] [-setup] [-hold] uncertainty 

After defining the clock, to take care of variance in the clock network clock uncertainty added. Clock uncertainty adds some margin of error into the system to account for variance in the clock network caused by non-ideality of clock network and clock source itself.

Above specified command can specify either inter-clock uncertainty or simple uncertainty. It sets uncertainty to the worst skew expected to the endpoints or between the clock domains. 


set_clock_uncertainty -setup 0.5 [get_clocks clk1]

set_clock_uncertainty -hold 0.2 [get_clocks clk1]

Clock uncertainty can also be added for rise and fall time of clock as bellow.

set_clock_uncertainty -max_rise 0.12 [get_clocks clk1]

set_clock_uncertainty -max_fall 0.12 [get_clocks clk1]

set_clock_uncertainty -min_rise 0.12 [get_clocks clk1]

set_clock_uncertainty -min_fall 0.12 [get_clocks clk1]

11. Clock latency:


set_clock_latency [-rise] [-fall] [-min] [-max] [-source] [-early] [-late] [-dynamic jitter] [-clock clock_list] delay object_list

Clock latency specifies the amount of delay for a clock signal reaching to the clock pin of a sequential element from the clock source pin. There are two types of clock latency one is network latency (default) and other is source latency (by using the -source option)

Clock network latency is the time taken by the clock signal to propagate from the clock definition point to the clock pin of a register. Whereas source latency is the time taken by a clock signal to propagate from actual-ideal waveform origin point to the clock definition point in the design. Source delay is also called an insertion delay.  


set_clock_latency 2.35 [get_pins ABC/XYZ/CP] 

12. Input delay:


set_input_delay delay_value [-reference_pin pin_port_name] [-clock clock_name] [-level_sensitive] [-network_latency_included] [-source-latency_included] [-rise] [-fall] [-min] [-max] [-add_delay] port_pin_list

Input delay defines the time requirements of an input port with respect to clock edge. Input ports are assumed to have zero input delay if it is not specified. The delay value to be specified is the delay between the start point and the object on which set_input_delay is being set relative to the clock edge.


set_input_delay -max 1.35 -clock clk1 {ain bin} 

13. Output delay:


set_output_delay delay_value [-reference_pin pin_port_name] [-clock clock_name] [-clock_fall] [-level_sensitive] [-network_latency_included] [-source-latency_included] [-rise] [-fall] [-min] [-max] [-add_delay] [-group_path group_name] port_pin_list

set_output_delay command sets output delay requirements on an output port with respect to the clock edge. Output ports are assumed to have zero output delay if it is not specified. 


set_output_delay 1.7 -clock [get_clocks CLK1] [all_outputs]

Above command will set output delay 1.7 unit to all output ports with respect to the positive edge (default edge) of the CLK1.

set_output_delay -max 1.4 -clock {CLK} [get_ports {Y}]

set_output_delay -min 1.0 -clock {CLK} [get_ports {Y}]

In above command -max value refers to the longest path and -min value refers to the shortest path. If no -max or -min value is specified, maximum and mimum output delays are assumed to be equal.

E.  Timing Exceptions

In this part, some of the important constraints like false paths, multicycle paths, maximum delay and minimum delay are defined. 

14. Multicycle paths: 


set_multicycle_path path_multiplier [-rise | -fall] [-setup | -hold] [-start | -end] [-from from_list | -rise_from rise_from_list | -fall_from fall_from_list] [-through through_list] [-rise_through rise_through_list] [-fall_through fall-through_list] [-to to_list | -rise_to rise_to_list | -fall_to fall_to_list] [-reset_path] 

A multicycle path is an exception of the default single-cycle timing requirement path. In a multicycle path, signal requires more than one single clock cycle to propagate from the start point to the endpoint of the path. This command specifies the number of cycles the data path must have for setup or hold check. The following command will set a constraint of two cycles path from source point A to endpoint B. 


set_multicycle_path 2 -from A -to B 

set_multicycle_path 3 -from C 

We can add a -through point between source and endpoint and also we can set multicycle path to all paths my mentioning only source or only endpoint. 

15. False paths: 


set_false_path [-rise] [-fall] [-setup] [-hold] [-from from_list | -rise_from rise_from_list | -fall_from fall_from_list] [-through through_list] [-rise_through rise_through_list] [-fall_through fall-through_list] [-to to_list | -rise_to rise_to_list | -fall_to fall_to_list] [-reset_path] 

A false path is a path that can not propagate a signal. For example, a path that never activates by any combination of inputs is a false path. False paths should be disabled for timing analysis. The SDC command set_false_path is used to define the false paths. False paths will be excluded for timing analysis. 


set_false_path -from U1/G -to U1/D 

set_false_path -from {ff12} -to {ff34}


This article has described 15 most important constraints in SDC file. There are many more constraints for a complex design. Here is the summary of all discussed constraints. 

1. SDC Version
2. Units
System Interface
3. Set driving cells
4. Set load
Design rule constraints
5. Set maximum fanout
6. Set maximum Transition
Timing constraints
7. Create Clock
8. Create Generated Clock

9. Group Path
10. Clock Uncertainty
11. Clock Latency
12. Input Delay
13. Output Delay
Timing Exception
14. Multicycle Path
15. False Path 

Thank you.

29 May

Antenna Effect in VLSI | Antenna Issue in Physical Design

Gate Oxide of a MOS transistor is the most sensitive part of a MOS device. Special care needs to be taken during fabrication of ASIC to protect it from any damages during fabrication steps and ASIC operation too. The antenna effect is a phenomenon that may cause damage to the gate oxide of MOS during the fabrication process especially due to the plasma etching process. In this article, we will investigate the antenna effect phenomena in detail and the reasons which are responsible for this effect.

What is the Antenna Effect?

The term Antenna Effect might not give you the right intuition about the actual effect it may lead you to think about electromagnetic radiation or transmitter-receiver concepts but here the case is different. So It has another popular name which is called "Plasma Induced Gate Oxide Damage" which provides the right intuition about the effect. As this name itself indicates that this is an effect caused by the Gate Oxide Damage due to the Plasma Etching process during the fabrication process of VLSI chips.  

Although the antenna effect occurs during the fabrication stage of the chip especially at the time of plasma etching but the prevention mechanism should be set in the physical design stage. The fabrication laboratory provides the antenna rule file which must be checked and designed should be cleaned as per the antenna rule during the physical signoff stage.

In fabrication flow first FEOL (Front End Of Line) is fabricated which involves the fabrication of all MOS transistors.  Once the FEOL fabrication is done BEOL (Back End Of Line) fabrication starts which involves the fabrication of metal interconnects. Antenna effect comes into the picture while BEOL fabrication. 

In IC manufacturing process Plasma etching process is used to fabricate the metal interconnects. Plasma etching is a dry and anisotropic etching process, used for selective etching. Plasma contains high energetic ions and radicals which get collected by the metal interconnects while the etching process of metals. Figure-1 shows the structure of MOS and collection of plasma by the interconnect.

Figure-1: MOS structure and plasma etching 

The amount of charge accumulation depends on the surface area of interconnect. These collected ions increase the potential of the interconnect and if the interconnect is connected to the poly gate, ultimately the potential of the gate will increase. Due to this increased potential of the gate, a drainage path may be formed through the gate oxide to substrate to balance this extra accumulated charge on the gate. If the amount of charge accumulation is high, this drainage path through the gate oxide may either breakdown the gate oxide which leads to permanent damage of MOSFET or may create charge trapping in the gate oxide which further leads to many side effects like early gate oxide breakdown, mobility degradation and threshold voltage shift. 

Gate oxide damage occurs basically due to plasma etching of interconnects connected to the gate, that's why this effect is also called "Plasma Induced Gate Oxide Damage" or "Antenna Effect". The metal interconnect which collects the plasma (ions) and is connected to the gate is basically termed as the antenna. Here it is important to know the fabrication process of interconnects which is explained in the next section.

Interconnects Fabrication Process

Over the polysilicon, a layer of dielectric is deposited and then cuts are made for the contact. Over the contact, Metal-1 is deposited and patterned and etched the extra metal and filled the whole region by the dielectric. Now before fabricating the metal-2, cuts are made in dielectrics for Via-1 and filled with Via-1 then over the via-1 Metal-2 is deposited. Again in the same way Metal 2 is etched and filled with dielectrics. This process is repeated as many times as the number of metal layers is there. At the end of all the metals processed, A PSG encapsulation is done as shown in the figure.

There are basically three steps are performed to process any metal layer after the corresponding via/contact is fabricated. 

  • Deposition

  • Etching

  • CMP

In the first step metal is deposited, In the second step the unwanted area of metal is etched away and in the third step, CMP (Chemical Mechanical Policing) is done.

Now let's talk more about the etching process. There are basically two types of etching processes is there, one is called wet etching with chemicals and the second is a dry etching with gasses. Dry etching provides complete anisotropic etching in which the lateral etching rate is zero. The most popular plasma etching is a dry etching process which is explained in brief in the next section. 

Plasma Etching 

Here the plasma etching process will be explained in brief just to understand the process. Plasma etching involves a high-speed stream of plasma of an appropriate gas mixture being shot at the sample. The plasma source is known as etch species are either charged ions or neutral atoms or radicals. During the etching process, plasma generates volatile etch products from the chemical reaction between the target material and the reactive species generated by the plasma. A basic setup of plasma etching has shown in the figure below.

Figure-3: Plasma etching setups

Figure-4: Plasma etching process in semiconductor fabrication

Both top and bottom electrodes are equal in size and parallel to each other. Bottom electrode holds the wafer and it is grounded. Due to the application of RF voltage and high pressure (P = 100mT to 1T) a plasma is set up between the two electrodes. High energetic electrons react with gas molecules and give various reactive species, neutral species and ions. Neutral species provide chemical etching and ions provides physical etching and a combination of reactive species and ions provides Ion Enhanced Etching.

We will discuss the prevention techniques of the Antenna effect in the next article. 

Thank you.

18 May

Latch-up Prevention in CMOS Logics

Before discussing the prevention techniques of Latch-up issue, let's recall the key factor of the latch-up issue first. Following two factors are important for the latch-up issue.
  • High resistance of n-well and p-substrate
  • β1 x β2 >  1 

                                                Figure-1: Latch-up formation

Figure-1 shows the parasitic BJT formation which causes latch-up. n-well and p-substrate resistance can be reduced by increasing the doping but it will degrade the device performance drastically.  But we can cut down the gains of parasitic BJT (β) and prevent the latch-up issue. Some popular techniques for latch-up preventions are as bellow.
  • Guard ring 
  • Well tap cells
  • Isolation trench
  • Epitaxial layer
  • Retrograde well doping 
  • Combination of epitaxial layer and retrograde well doping
  • FDSOI Technology
  • ESD protection techniques

1. Guard ring:

                                                        Figure-2: Guard Ring

If Vout goes bellow the VSS and the diode between drain and p-substrate of nMOS become forward bias, electrons from drain start injecting from to substrate and collected by the body of pMOS. This cause a current from in the opposite direction of electron flow. which ultimately triggers the Qp transistor as shown in the figure-1. Now to break this chain, two sets of n+ implant in n-well, p+ implant on p-substrate added in between nMOS and nMOS as shown in the figure-2. These will collect the electrons injected from the drain of nMOS and prevent the current flow from the drain of nMOS to the body of pMOS. Which stops triggering the Qp BJT.
Similarly in case of the Vout goes above the VDD and drain of pMOS start injecting holes in n-well and goes and collected by the body of nMOS. This lead to the trigger of Qn BJT. But by adding the guard ring these holes will be collected by the guard ring and stop the latch-up.

2. Well tap cells: 

In tapless standard cell design to prevent the latch-up, we need to tap the n-well to VDD and p-sub to VSS. These well tap cells tap the n-well to VDD and p-sub to VSS. Figure-3 shows the crosssection of tapless cell and figure-4 show the layout of well tap cell and tapless standard cell.

                                        Figure-3: Cross-section of tap and tapless cell

Figure-4: Layout of tapless cell and well tap cell

The well tap cells are placed in the standard cell row in the regular interval as per the maximum distance rule define in technology library. 

3. Oxide trench isolation: 

In this technique, nMOS and pMOS have insolated using the buried oxide and oxide trench. A horizontal buried oxide created deep inside and vertical oxide trenches are created later and connected both together to separate the n-well and p-substrate. The oxide trenches are isolator in nature so oxide trench stops the formation of the PNPN device. A cross-section of oxide trench isolation is shown in the figure-5.

Figure-5: Crosssection of a trench isolation

4. Epitaxial Layer: 

In this technique, a low doped p-epitaxial layer (known as P-) grown over the P-substrate (called P+). The P- epitaxial layer provides a low impedance path for minority carrier which prevents the latch-up triggering. This technique is also called P on P+. A cross-section epitaxial layer has shown in the figure-6.

Figure-6: Crosssection of CMOS using epitaxial layer

The only problem with this technique is, it's a sophisticated process to grow the epitaxy layer. Another alternative is we can use the epitaxy wafer for this purpose.

5. Retrograde Well Doping : 

In normal n-well doping process, the doping concentration is highest at the surface and it decreases as the depth of well increases. But in the retrograde well doping process, there is very precise control of doping concentration over the depth and we have peak doping concentration at deep inside the n-well, not at the surface. A doping profile of normal doping and retrograde well doping is shown in figure-7.

                                                Figure-7: doping profile of retrograde well doping

A retrograde well doping is done at the bottom of normal n-well as shown in the figure-8. This region has a high doping concentration and creates a low resistance path. The body connection which is taken from N+ doping is extended to this high dopped region. So there is the formation of low resistive path bellow the n-well which stops the triggering of PNPN device. A cross-section view of retrograde well doping has shown in figure-8.

Figure-8: Retrograde well-doped CMOS

6. Combination of the epitaxial layer and retrograde well doping : 

We can use a combination of the epitaxial layer and retrograde well doping together both the techniques together which is also a very effective way to prevent the latch-up issue but the process is a bit complex.

7. SOI Technology : 

In SOI (Silicon on Insulator) technology an oxide layer comes bellow the source-drain doping and stop the parasitic BJTs formation. So SOI technology completely eliminates the latch-up issue. A cross-section of CMOS in SOI technology has shown in figure-9.

                                            Figure-9: CMOS in SOI Technology

We can use a combination of the epitaxial layer and retrograde well doping together both the techniques together which is also a very effective way to prevent the latch-up issue but the process is a bit complex.

These are the ways to prevent latch-up in CMOS technology. Each technique has its own pros and cons. 

Thank You!

Standard Cells in ASIC Design | Standard Cells in VLSI

Standard cells are well defined and pre-characterized cells used in ASIC (Application Specific Integrated Circuit) Design flow as basic building blocks. All these cells are equal in height and can easily fit into the standard cell row. Standards cells are highly reusable and save lots of ASIC design time.

Standard Cell Layout

All the Standard cells are in equal in height and varying width. Main characteristics of a standard cell have been explained with the help of the following figure.

   Figure-1: Standard Cell layout style

At the top of the standard cell, there is VDD rail and bottom there is a VSS rail. Both the Power rails are drawn in the Metal-1 layer. In between the VDD rail and VSS rail there are three main regions, a nwell region, a gap of nwell and pwell and pwell region. nwell region is near to the VDD rail and pwell region is near the VSS rail. pMOS transistors are build inside the nwell, so all the pMOS transistors are in the top half of the cell and similarly, all nMOS are in the bottom half of the standard cell.

Layout of a schematic can be drawn in various ways. For example layout of a NAND gate can be drawn in following two different styles. 
 Figure-2: Schematic of a NAND gate

 Figure-3: Layout of a NAND gate

 Figure-4: Layout of a NAND gate

Figure-2 is showing the schematic of a NAND gate and figure-3 and figure-4  showing two different layouts of the schematic shown in the figure. In figure 3 both the nMOS are in not the same level, they are stacked but in the layout of figure 4 all nMOS are in one level and all pMOS are at one level. And in figure-3 gates are drawn horizontal and not common in nMOS and pMOS. But in figure-4, all the poly gates are drawn vertical and common to nMOS and pMOS both. 

There are many reasons f0r preferring a layout style like in figure-4. Some of them are:

1. Save Design Area: Both the nwell and pwell are in the same level for all the standard cell, so they can easily abut and make a common well which saves lots of areas.
2. Easy placement for APR tool: All the standard cells have the same height and easily can be fit into the standard cell row so make it easy for APR (Automatic Place and Route) to place them. They also have power rails in the same location for all the standard cells, so power rails can also be abutted easily. 
3. Easy to route: All the pins of standard cells are in the intersection of horizontal and vertical tracks, So it becomes easy to route them by the APR tool

Tracks in standard cells:

Track can be defined as a line on which metal layers are drawn. A track means one M1 Pitch. Height of Standard cell is generally measured in term of no. of tracks inside it. like a 6T standard cell means that the height of the standard cell is 6 Track of M1. An example of 13T standard cell is given below in figure-5.

Figure-5: A 13T height standard cell

In the above example, the height of one track is 190 nm. So total height of cell is  13T = 2470 nm (13 x 190) and width is 5T = 950 nm (5 x 190).    

Various heights standard cell library:

Generally, there are various sets of standard cell library having different track size of standard cells. Depending on the use of ASIC, track height a standard library has selected. There are generally three sets of standard cell library characterized as small transistor standard cell, large transistors standard cell and medium transistor standard cell. An example for 6T, 12T and 9T size standard cells are shown below.

Figure-6: Various height's of standard cell 

Small transistor standard cells are used for high-density design and these cells having low power consumption. Large transistors standard cells large area but having very good performance. Medium transistors standard cells have a balance between large transistors and small transistors. So there is a tradeoff between area/power vs performance. A comparison has been shown below in figure-7.

Figure-7: Tradeoff between performance and area for various heights standard cell

Various applications of these cells are as bellow.

  • Small transistor cells (6T Cells)
    • Minimum area and low power
    • Mobile applications
    • Ultra-low-power applications
    • Embedded microcontroller
  • Large transistors cells (12T Cells)
    • Large area
    • High performance and speed
    • High-speed computing 
    •  Critical blocks
  • Medium transistors cells (9T Cells)
    • Balance area and performance
    • General Computing
    • GPU
    • General-purpose circuit

Thank you!