05 November

Input Files Required for PnR and Signoff Stages

In this article, we are going to discuss the input files required in various stages of pnr and signoff. We can categories the set of inputs into two parts, one is mandatory and the other is an optional set of inputs.

A. Place and Route stages:


I. Pre Placement Stage

    • Gate level netlist 
    • Logical Library
    • Physical Library
    • SDC file
        Optional inputs
    • Block partition def
    • Pin def
    • Power plan script
    • Welltap placement rule
    • Macro placement guidelines
    • MMMC Setup file
    • EndCap, Decap cell list
    • Spare Cell module definition and rule
Note:  (i) Logical Library, Physical Library and SDC file will be required in each stage.
            (ii) Netlist will get modified in each stage and an updated netlist will be used in the next stage. 

II. Placement

    • Preplace database
        Optional Inputs
    • Placement blockage script
    • Path groups script
    • Placement setting script 
    • Timing and Congestion Optimization scripts
    • Clock tree constraints (In case of Early Clock Flow)


    • Placement database
    • Clock tree constraints

IV. Route

    • CTS database

V. Chip Finish

    • Route database
    • Filler cell list

B. Metal Fill

    • OASIS/GDS of Chip finish stage

C. RC Extraction

    • ICT File / Quantus Techfile (qrcTechFile)
    • MMMC setup file
    • LEF
    • DEF
    • Merged OASIS/GDS file

D. IR Analysis

Technology/Library Data

    • LEF file (.lef)
    • LIB file (.lib)
    • Technology file (.tech)
    • GDS file of standard cells (.gds)
    • GDS Layer map file
    • Device model file*
    • SPICE Netlist of Standard cells* 

Design Data

    • DEF file
    • Netlist file
    • SPEF file
    • STA File*  (Timing Window, slew, instance frequency, clock domain info)
    • VCD file*
    • PLOC file*
* Files required only for dynamic analysis 

Types of Analysis:

I. Static IR Analysis

II. Dynamic IR Analysis

III. EM Analysis


E. Static Timing Analysis

  • Design Netlist 
  • SDC
  • LIB
  • SPEF
  • MMMC view definition file

Optional inputs:

  1. Instance-based IR drop file
  2. SI library
  3. Base/Incr Delay annotation file

F. Physical Verification


    • Merged GDS file
    • DRC RuleDeck file 

II. Antenna

    • Merged GDS file
    • Antenna RuleDeck file

III. Layout Vs Schematic Check (LVS)

    • PD Netlist
    • Merged GDS file 

IV. Logic Equivelence Check (LEC)

    • Golden Netlist
    • PD Netlist
    • LEC Constraints (if any) 

 In case you find anything missing or need a correction, please let me know in the comment section.

Thank You!

25 September

TSMC 7nm, 16nm and 28nm Technology node comparisons

Before starting this article, I would like to say this topic is highly sensitive and we are not supposed to reveal any foundry data. So Instead of making comments on any data which you know and I have not given here, you may mail me along with the reference link. The purpose of writing this article is only to make aware to new people who are preparing to enter into VLSI industry in an easy way. 

Kindly note that none of the data is being added from our side in this article which is not available in the public domain. You will notice that many fields I have left blank intentionally, which you may know but the foundry has not reviled those data in the public domain. 

So this article is just a collection of various data available on different websites instead of any data from my side. I will provide all the references at the end of this article, from where I have collected this information. I took all the care to maintain confidentiality but if anything you found is not appropriate to publish, please let us know through email.

Below image may help you to understand various parameters of FinFET. This image is taken from https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7nm-and-the-snapdragon-855-dtco/

Figure: FinFET structure and dimensions

S.N Parameters 7nm 16nm 28nm

A. Transistor wise

1 Transistors 4th Gen FinFET FinFET Planner MOSFET

2 Gate Length (Lg) 16 nm 34 nm 24 nm

3 Fin Width (Wfin) 6 nm NA

4 Fin Heigth (Hfin) 52 nm 37 nm NA

5 Fin Pitch (Pfin) 30 nm 48 nm NA

6 Contacted Poly Pitch (CPP) 57 nm (HD)
64 nm (HP)
90 nm 117 nm

7 W effective 3.66

8 Minimum Metal Pitch (MMP) 40 nm 64 nm 90 nm

9 Standard Cell Height 240 nm (6T)

10 Transistor Density 91.2 M/mm2 28.9 M/mm2

11 6T SRAM bit cell size 0.027 um2 0.074 um2 0.127 um2 (HD)

12 Contact Trench Fill Cobalt Tungsten

13 Opertating Voltage 750 mV 800mv and 1V

B Metal wise

14 Total Metal Layers 17 10

15 Double Patern Layers 7 (Fin, Poly, M0, M1, M2, M3, M4)

16 Patterning Fins (SAQP)
Poly to M4 (SADP)
Rest Single

17 DUV/EUV 193nm DUV + 13.5nm EUV 193nm DUV 193nm DUV

18 Via Pillers Yes No

19 PG Routing Dual M1 PG Structure

C General

20 Mass Production Year Q2 2018 2015 Q4 2011

21 Speed Improvement 30%, comapre 16nm with same power

40% , compare to 28nm with same power

22 Power Reduction -55% compare to 16nm with same speed

-55% compare to 28nm with same speed

23 Density 3.3X compare to 16nm

24 Cut metal Area reduction through
Cut metal layers.
Routers are cut metal aware



24 September

Top 20 TCL syntax helpful to improve TCL scripting skill for VLSI Engineers

One scripting language without which it will be very difficult to survive in VLSI Industry, that would definitely  be TCL (Tool Command Language). TCL is widely used everywhere in the VLSI industry because many tools are based on the tcl. We can directly interact with the tool using tcl CLI (Command Line Interpreter). 

It has been observed that many beginners initially hesitate to start the TCL scripting. Most of the cases user know the basic tcl commands but how to connect all them and create a script is the only problem. I would say even you know some basic tcl commands you can start writing your own script for your day to day requirements. Most important this is BEGIN the process of writing the script. Here I am presenting 20 common tcl syntax which I use frequently in my tcl scripting and hope it will help you to break the ice. Improvement and prefection will come as you practice but start is the most important. These 20 syntax will definitely help you lot to start and improve your tcl scripting a lot. 

1. foreach loop

Where we have to iterate on each element on a list of elements and have to perform some operation on each element.
foreach var $Var_list {
//operations for each $var
Supposed we want to print all the macros instance name, reference name and total count of macro in a block.
set macros [dbGet [dbGet top.insts.cell.baseClass block -p2].name]
set i 0
foreach macro $macros {
set refName [dbGet top.insts.name $macro -p].cell.name
puts "$macro - $refName "
incr i
puts total macro count = $i

2. Nested foreach loop

If we have to iterate on each element of a list and then further we need to iterate on each parameters associated with the element.
foreach i $list1 {
    //list2 is derived based on $i
    foreach j $list2 {
        //operations on $j
Suppose we have to find the list of feedthrough pins and the total numbers of feedthrough pins in each edge of a rectilinear block. A script can be written like this for that.

set edges [dbget top.terms.edge -u]
set i 0
foreach edge $edges {
    set j 0
    foreach pin [dbget [dbget top.terms.edge $edge -p].name ft* ] {
        puts "$edge $pin"
        incr j
    puts "$edge : total ft pin count = $j"
    incr i
puts "Toal edge of block = $i"

3. for loop

Where we want to repeat a loop in between a certain start and endpoint with a certain increment
for {initialization}{condition}{increment} {
Suppose we want to know the metal layer's width and pitch of all metal from M5 to M10 in innovus tool.

for {set i 5}{$i <= 10}{incr i}{
    set width [dbGet [dbGet top.head.layers.name M{$i} -p].minWidth]
    set pitch [dbGet [dbGet top.head.layers.name M{$i} -p].pitchX]
    puts "M{$i} $width $pitch"

4. Nested for loop

Same as above example only syntax change and one loop in running inside another loop.
for {initialization}{condition}{increment} {
    for {initialization}{condition}{increment} {

5. while loop

When we need to repeat a loop until a particular condition is true.
while {condition} {
Suppose we need to read all the lines of a file one by one and store is a variable dynamically.

set fp [open my_report.tcl r]
while {[gets $fp data] >= 0} {
    if {[regexp "VIOLATED" $data]} {
        //desired statement for operation

6. if-else conditions

When we want to do something if certain condition is true. We can either put else statement or skip it.
if {bolean_condition} {
} else {

Suppose we need to convert SVT cell to ULVT cell.

if {[regexp SVT $cell_ref]} {
    set eco_ref [regsub {SVT} $cell_ref "ULVT"]

7. if-elseif... else condition

When we want to check another if condition if one prior if condition is not true.
if {bolean_condition} {
} elseif {bolean_condition} {
} else {

Suppose we need to read a report file inside a script and generate an eco file in which if there is Weak Driver then need to upsize the driver from D1--> D3, D2-->D4 and D3-->D5. We can write script as follow.

set fp [open existing.rpt r ]
set fp1 [open new_ecofile w+]
while {[gets $fp data] >= 0 } {
    if {[regexp "Weak Driver" $data]} {
        set inst [lindex $data 7]
        set cell [lindex $data 8]
        if {[regexp D1BWP $cell]} {
            regsub "D1BWP" $cell "D3BWP" newCell
        } elseif {[regexp D2BWP $cell]} {
            regsub "D2BWP" $cell "D4BWP" newCell
        } elseif {[regexp D3BWP $cell]} {
            regsub "D3BWP" $cell "D5BWP" newCell
        if { [ info exists newCell ]} {
        puts $fp1 "ecoChangeCell -inst {$inst} -cell $newCell"
close $fp
close $fp1

8. Arithmetic operations

When we need to add/subract/multiply/devide some numbers

set s [expr $a + $b + $c]
set d [expr $a - $b ]
set m [expr $a * $b]
set d1 [expr $a / $b ]


If we need to know, how much space will take a 4X, a 8X and a 16X decap cell together.

set cell4X [dbget [dbget head.libCells.name $decap4 -p].size_x -u]
set cell8X [dbget [dbget head.libCells.name $decap8 -p].size_x -u]
set cell16X [dbget [dbget head.libCells.name $decap16 -p].size_x -u]
set distX [expr $cell16X + $cell16X + $cell4X]
puts $distX

Note: Be careful like in the following cases

>expr 3/2

>expr 3/2.0

9. regexp

To match the regular expression. Regular expression has a wide list, we will see only few which we use mostly.
Syntax :
regexp {pattern} $string
Suppose we want to change the D1, SVT cell to D2, LVT we can check the cell with regexp and then we can perform regsub for substitution and generate an eco file.

if {[regexp {D1BWP240H11.*PDSVT} $clock_cell_ref]} {
    regsub {D1BWP240H11} $clock_cell_ref {D2BWP240H8} new_clock_cell_ref
    regsub {PDSVT} $new_clock_cell_ref {PDLVT} new_clock_cell_ref
    puts $fp_w "ecoChangeCell -inst $clock_cell -cell $new_clock_cell_ref"

10. regsub

To substitute the regular expression
regsub {old_pattern} $string {new_pattern} new_string_name
As explained in the regexp section

11. Reading a file

Many times we have to read a report file inside the tcl scripting to make some fixes based on the violation reported. We read the file line by line and store the data in a file pointer variable dynamically.
set fp [open existing_file_name r]


we can read a file line by line in a variable like this.

    set fp1 [open $old r]
    while {[gets $fp1 data] >= 0 } { 
         // $data variable will get string line by line of old file
    close $fp1

12. Writing a file

We can write a file and close that as follow.

set fp2 [open $new w+]
puts $fp2 "Whatever we want to write in file will go line by line"
close $fp2

13. proc

If we need to use a few lines of code, again and again, we can make a proc using those codes and can call easily by the proc name. No need to write code every time.
proc proc_name {} {
// lines of code

If we need to find the basic details of a block, we can write a proc something like this.

proc blockInfo {} {
    puts "Block name: [dbget top.name]"
    puts "All Layers: [dbget head.layers.name]"
    puts "Block Area: [dbget top.fPlan.area]"
    puts "Box size: [dbget top.fPlan.box_size]"
    puts "Boxes: [dbget top.fPlan.boxes]"
    puts "Toatl pins: [dbget top.numTerms], Inputs - [dbget top.numInputs], Outputs -                    [llength [dbget top.terms.isOutput 1 -p]]"
    puts "Macro Count: [llength [dbget top.insts.cell.baseClass block -p2]]"
    // Many more parameters can be added

We just need to source above file and call the proc blockInfo proc, it will display all the above info of block.

14. proc with arguments

Sometimes we need to pass some arguments in proc and we want the result of proc based on user argument.
proc proc_name { arg1 arg2 arg3 ...} {
    // lines of code
proc_name arg1 arg2 arg3

Suppose we want to write a general proc in which if we pass the net_name, it should return the net_length of that particular net. We can write that as follow.

proc netLength {net_name} {
    set net_length 0
    set net_wires_length [dbget [dbget top.nets.name $net_name -p].wires.length]
    foreach i $net_wires_length {
        set net_length [expr $net_length + $i]
    puts $net_length

 We can also set a default value of the proc argument. So in case the user does not pass the argument value, proc will take the default value.
proc proc_name {{arg1 10} {arg2 20}} {
set a $arg1
set b $arg2
// More statements

So if we call the proc like
it will take the default value of arg1 and arg2 and will set a 10 and set b 20.

But if we call this proc like
proc_name 50 
It will set a 50 and b 20

we can also call like
proc_name 50 45 
In the above way  proc will set a 50 and b 45

15. exec

To use bash command inside tcl script
exec date

set timestamp_prefix [exec date +%m%d_%H_%M]

16. dbGet/dbSet/dbQuery

These are the innovus tool-specific commands, and widely used in innovus tool related scripting.
Syntax and Examples will be discussed in a separate article.

The link will made available here [Not now].

17. list operations

There are various list operations, all are important in various way and frequently used.
llenght, lappend, lindex, lreplace, lset, lsort etc.

Kindly do the man command for more details

18. alias

To shorten a long command or a command with its switches to a short command.
alias short_commad "original_commad"

alias si "selectInst"
alias sn "selectNet"

19. grep

To find the particular pattern
exec grep "pattern" $file_name
egrep and zgrep are also used in place of grep.

Will discuss in details in a separate article
Link [Not now]

20. sed

sed is called stream editor, it can do lots of tasks. we use generally sed to replace or delete a particular pattern in a file or string.
exec sed 

If we want to replace a line having particular unique pattern completely by another line . We can do that like folow.

exec sed -i "s|Pattern .*|$new_line|" $file_name

Example 2:
If we want to write some lines of code which are stored in a file just after a line having some uniqe pattern. we can do that as follow

set num [exec sed -n "/^Source Script.*/=" $file_name ]
incr num
exec sed -i "$num r $script_file" $file_name

Example 3:
If we want to delete all lines having a unique pattern

exec sed -i "/DEL*/d" $file_name

Note: grep, sed and awk is a very handy command for various operations, these commands has explained in more details in the following article.
Link [Not available now]

Thank You.

08 September

Interview questions for experienced Physical Design Engineer, Question set - 9

Code: CDN4Y072021PD

Experience level: 4 Year
Profile: Physical Design Engineer

1. Introduction and physical design experience
2. What major differences have you observed in the 7nm and 14nm process nodes?
3. What is the functionality of this circuit? (He drawn schematic in paint)
4. Do you think, is there any issue with the above circuit? If so what would you suggest for improvement?
5. When clock gatting circuit has added in the design RTL/Synthesis/PnR?
6. What are the checks you perform before starting the floorplan?
7. What is a library check?
8. What are the information available inside the .lib file?
9. How is the timing of a cell defined in .lib file?
10. What if the .lib file is missing but .lef file is available for a cell? and similarly, if .lef file is missing but .lib file is present for a cell?

11. How do we define the core area for any block?
12. How do we decide the height and width of a block?
13. What are the guidelines we need to follow in macro placement?
14. Is there any rule for abutting the macros?
15. What steps exactly tool does in the placement stage?
16. Why do we use boundary cells?
17. Why can't we use placement blockage at the end of each row in place on the boundary cell?
18. What was the target latency in your block and what has been achieved?
19. Can you explain the ccopt method?
20. Which flavour of Vt cell you used in the clock tree?

21. Which type of derating you have been used in your different projects?
22. Why do we start using POCV when we had AOCV derate?
23. What is the shielding of a net? How it works?
24. Have you used shielding in your block?
25. What is NDR?
26. What is the difference between shielding and NDR? Can we use only one of these two?
27. Where did you placed the clock gating cell, near the sink or source?
28. Can you tell me the advantage and disadvantages of placing ICG near the sink and near the source?
29. What is CPPR?
30. (A diagram has been drawn in paint as shown below) In this diagram can you tell me between which edges the setup and hold timing will be checked?

31. If we change the scenario like below, Now between which edge setup and hold will be checked? 
32. What is internal power and switching power?
33. What is the impact of the threshold voltage of a cell on the internal power and switching power?
34. What is the impact of IR drop in cell delay?
35. How do you fix the static IR drop?
36. What was the limit of dynamic IR drop in your recent project?

28 August

Flip-flop and Latch : Internal structures and Functions

The flip flop is the most commonly used sequential element in any ASIC design, especially the D-type flip-flop. In the D flip flop, the D indicates delay, which means the output is a delayed version of input D.  Whereas a latch is the simplest and a basic sequential element. In general, there are two latches used to make a flip flop. the flip-flop is sensitive to clock edge and the latch is sensitive to clock level. The following section will explain the internal structure and operation of flip flops and latch. In this article, we will limit our discussion to only d type flip flops and d type latch which are most common in ASIC design. 

Schematic of the latch and flip-flop

The simplest design latch and flip-flop both are having 3 pins, One input data pin (D), one input clock/enable pin (CP/E) and, one output pin (Q). There could be a set and reset pins also but here for simplicity we are not including those in our discussion. The symbolic representation of a latch and a flip flop has been shown in figure-1.

Figure-1: Symbolic representation of Latch and flip-flop

In figure-1, the symbol of a posotive level sensitive d-latch and a positive edge triggered d flip-flop has shown. In negative latch and flip-flop only a dot appears before the E/CP pin. At a high level, we can think that latch and flip flop in terms of 2:1 multiplexer. A latch can be realized using a 2:1 multiplexer whereas to realize a flip flop, two multiplexers are required. Figure-2 showing the architecture of positive level sensitive d-latch and a positive edge triggered flip flop in terms of multiplexers.

Figure-2 : A positive d-latch and flip-flop using multiplexer

In a positive level sensitive latch the output is fed to I0 input of multiplexer as shown in figure-2. In same way in a negative level sensitive d-latch the output Q is fed back to input I1. A positive edge triggered d-flip flop is made of two negative level sensitive d-latch connected back to back. In case of negative d flip flop two positive level sensitive d-latch would be required. If we dive deep inside the multiplexer and go to the transistor level, we will find the transistor level schematic of a positive level sensitive d-latch and positive edge triggered d flip-flops as shown in figure -3.

Figure-3.a : A positive level sensitive d-latch using transmission gates

Figure-3.b: A positive edge triggered d flip-flop using transmission gates

A 2:1 multiplexer is made of two transmission gates and a transmission gate is made using a pMOS and an nMOS transistor as shown in the above figure. A latch is having two transmission gates in which the input of one transmission gate is connected to the output. A flip flop is made of two latches (that is four transmission gates) connected back to back as shown in figure-3. From the above figure, it is clear that a flip flop is having more transistors (double) as compare to a latch and hence a flip flop is having double the area as compared to the latch. The understanding of the working of latch and flip-flop is the most important part which will be discussed in the next section.

Working of a d- latch

The working of a positive level sensitive d-latch only is discussed here with the help of input and output waveform. The working of flip-flop will be discussed in the next section.

Figure-4: Input-Output waveform of latch

There are two transmission gates are used in a d-latch. In case of a positive level sensitive d-latch the output is feedback to the input of TGO transmission gate. Transmission gates are made of a nMOS and a pMOS as shown in above figure and it is being controlled by the enable signal E which is actually the clock signal. When the enable signal is high, the nMOS and pMOSof TG1 is in on state and at the same time, both transistors of TG0 are in off state and vice-versa happens when the enable signal is low. There is a direct path established from pin D to pin Q when the Enabe signal is high and it is called latch is in transperent state. But when enable signal goes low, TG1 gate is in off state and a feedback loop is established between Q to input of TG0 which insures that there is no change in output Q irrespective of changes in input pin D, which is termed as latch state. Figure-5 shows when the latch is transperent and when it is latched through the waveform. 

Figure-5: Working of a positive level sensitive d latch.

The working of a positive level sensitive d-latch is straight forward, it keep passing the input D to Q when its enable signal E is high and and it keep the output Q unchanged when enable signal is low. Same can be seen in figure-5, only output changes when input changes and enable signal is high.

Working of a d flip-flop

In a positive edge triggered d flip flop, there are two negative level sensitive d latch connected back to back and the second latch is having inverted enable signal as compare to first latch. This inverted enable signal to second latch makes sure that both the latch  never goes transperent or latched state simultaneously. A typical input output waveform has shown in figure-6 for better understanding.

Figure-6: Input output waveform of a positive d flip-flop

Lets consider the the case when the clock signal is low, the first latch is transperent and input D is transmitted up to QM point. But at the same time second latch will be in latched state because it gets inverted clock signal so the output Q is latched with QM. There is no chance the outupt Q will get changed in this duration.

The next moment when clock signal transits from low to high, the first latch will go from transperent mode to latched mode and second latch will go from latched mode to  transperent mode. So during the clock transition from low to high, whatever signal is sampled at QM previously gets transferred to the output Q.

The next moment when clock signal goes to high, there is not transfer of input signal D anymore and Wahtever signal previously samples at QM will be available at output Q.

The next moment when the clock signal transits from high to low, first latch will trasit from latched to transparent mode and second latch will transit from transparent to latche mode. So at this edge of clock transition there will be no change in output.

The operation of positive d flip flop can be summarized as, the output changes only at the rising clock edge and at this moment input D is trasfered to output Q and all other moment output is remain unchanged. So it is better in terms of avoid glitch as comapare to latch but more in area and more prone to process variation. For detailed operation and comparison please watch this playlist.

Thank you.

23 August

Tie Cells in Physical Design

The tie cell is a standard cell, designed specially to provide the high or low signal to the input (gate terminal) of any logic gate. The high/low signal can not be applied directly to the gate of any transistors because of some limitations of transistors, especially in the lower node. The limitation will also be discussed along with the schematic and operation of tie cells in this article. We will discuss the following sub-topics in this article.

  • Need of tie cells
  • Schematic of tie cells
  • The function of tie cells
  • Placement of tie cells

Need of tie cells:

In the lower technology node, the gate oxide under the poly gate is a very thin and the most sensitive part of the transistor. We need to take special care of this thin gate oxide while fabrication (associated issue is antenna effect) as well as in operation too. It has been observed that if the polysilicon gate connects directly to VDD or VSS for a constant high/low input signal, and in case any surge/glitch arises in the supply voltage it results in damage of sensitive gate oxide. To avoid the damages mentioned above, we avoid the direct connection from VDD or VSS to the input of any logic gates. A tie cell is used to connect the input of any logic to the VDD or VSS.

Figure-1: Need of tie cell

There are two types of tie cells.

  • Tie-high cell
  • Tie- low cell

As the name suggests, the tie-high cell's output is always high and the tie-low cell's output is always low.  

Schematic of tie cells:

The tie cell has no input pin and only one output pin. The output of the tie-high cell is always high and the output of the tie-low cell is always low and it is the glitch-free output that connects to the input of any logic gates. The schematic of tie high cell and tie-low cell is shown in the figure-2.

Figure-2: Tie-high and tie-low cells

In the tie-high cell, the drain and gate of nMOS are shorted together and connected to the gate of pMOS, and output is taken from the drain of pMOS. Whereas in the tie-low cell the drain and gate of pMOS are shorted together and connected to the gate of nMOS and output is taken from the drain of nMOS. The function of these schematics is explained in the next section.

Function of tie cells:

Both tie-high and tie-low cells have similar working. Here working of the tie-high cell is explained. A similar logic can think for tie-low cell. From figure-2 tie-high cell, the drain and gate of nMOS are shorted.

So Vg = Vd
==> Vgs = Vds
Therefore, Vds > Vgs -Vt

This shows that the nMOS will always be in the saturation region. The configuration of MOS where drain and gate are shorted is popularly known as a diode-connected transistor. And when nMOS is behaving like a diode here, the gate of pMOS is always low and so pMOS is always in on state. When pMOS is in on state its drain which is output will always be high.

Similarly, for the tie-low cell, the pMOS is always in saturation region so the gate of nMOS is always high and hence the drain of nMOS will always be at the low logic.

One more important thing is here that the sudden spike in VDD or VSS will be not propagated to the output of the tie cell.

Placement of tie cells:

Tie cells are not present in the synthesized netlist and not placed in the initial placement of the standard cells. Tie cells are inserted in the placement stage and more specifically at the final stage of placement. Where ever netlist is having any pin connected to 0 logic or 1 logic (like .A(1'b0) or .IN(1'b1), a tie cell gets inserted there. Click here to read more about the placement stage and the order where the tie cell get inserted in the placement stage.

Thank you.